This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-182590, filed on Jun. 24, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to a pulse generation circuit that generates an output pulse in response to an input pulse, and more particularly to a pulse generation circuit that can shorten the output pulse cycle.
2. Description of the Related Art
In semiconductor memories such as static RAMs, the word drive circuit for driving a word line is a pulse generation circuit that generates an output pulse to the word line having a relatively heavy load in response to a predetermined control pulse. When receiving a control pulse acting as a trigger, the pulse generation circuit generates an output pulse having a higher drive capability through multi-staged inverters. The last stage of the pulse generation circuit consists of large-sized transistors to output the output pulse by driving an output load with its high drive capability. To drive the large-sized transistors in this output stage, a drive pulse having a larger drive capacity is generated from the control pulse by the multi-staged inverters.
FIG. 1 illustrates a conventional pulse generation circuit. FIG. 2 illustrates the operational waveforms of the pulse generation circuit shown in FIG. 1. The pulse generation circuit acting as a word line drive circuit drives a word line (not shown) connected to an output terminal OUT, in response to the control pulse at a node n1 input into the pulse generation circuit. The word line is selected by raising the output terminal OUT and the word line returns to the non-selected state by falling the terminal OUT.
To drive the output terminal OUT having a large load capacitance, the size of the transistors in an inverter INV3 at the output stage are made large. The control pulse is propagated being gradually converted into a pulse having a larger drive capability by multi-staged inverters INV1 and INV2. The inverter INV3 in the last stage is driven by the drive pulse generated at a node n3 and having a relatively large drive capability.
The function desired to the word line drive circuit is the function for raising its output terminal at a timing as immediately from the leading edge (the rising edge in FIG. 2) of the control pulse as possible. On the other hand, it is not preferable to make the size of the transistors in the inverter of each stage larger to reduce the delay time period: because each of input load capacitance C1, C2 and C3 accompanying each inverter is also made larger and the propagation time period of the pulse becomes rather longer, and, therefore, the time period between the generation of the control pulse and the generation of the output pulse at the output terminal is made longer.
Therefore, in the conventionally proposed pulse generation circuits, the sizes of the transistors in each inverter are made imbalance. Taking an example of FIG. 1, the size of p-channel transistors P1 and P5 is made large and the size of n-channel transistors N2 and N6 is made small in the inverters INV1 and INV3, and the size of a p-channel transistor P3 is made small and the size of an n-channel transistor N4 is made large in the inverter INV2. In this specification N means n-channel transistor and P means p-channel transistor. By arranging the sizes of the transistors as described above, the leading edge (the edge denoted by the arrow in the FIG. 2) of the control pulse at the node n1 can be propagated to the next nodes n2 and n3 without delay and the delay of the rise edge of the output terminal OUT can be minimized. Furthermore, since the size of one transistor is large and that of another is small in the inverter in each stage, the gate capacitance C1, C2 and C3 being the input load capacitance can be decreased and the delay of propagation of a pulse can be minimized by decreasing the input load capacitance of each inverter.
However, in the above pulse generation circuit consisting of imbalance inverters, the size of the drive transistors in each stage for the trailing edge of the control pulse is small and the drive capability of those transistors is small. As a result, the slopes of the trailing edges at the nodes n2 and n3 are more gradual.
When the fan-out, i.e. the ratio of the output drive current to the output load to drive, of a transistor, such as the transistors P1, N4 and P5 shown in FIG. 1 is small, the influence on the delay time period of the pulse caused by the process variation of the transistors is small. On the other hand, when the fan-out is large such as the transistors N2, P3 and N6, the influence on the delay time period of the pulse caused by the process variation is large. As a result, trailing edge at each node corresponding to the trailing edge of the control pulse may be delayed considerably by the process variation as indicated by dt in FIG. 2.
Since a trailing edge is an edge for the non-selected side, a small delay does not matter. However, pulse generation circuits in recent years have been demanded to narrow the time between the output pulses OUT. For example, in a word line drive circuit of an SCRAM, it is demanded to improve the performance of whole read and write operation by shortening the cycle for driving the word line. Therefore, it is necessary to advance the timing of the leading edge (rise edge) of the output pulse OUT as well as to avoid a delay, which depends on process variations, of the trailing edge (fall edge).
FIG. 3 illustrates another conventional pulse generation circuit. FIG. 4 illustrates the operational waveforms of the pulse generation circuit shown in FIG. 3. The pulse generation circuit shown in FIG. 3, which is an improvement of the one shown in FIG. 1, drives a NOR gate 10 at the last stage by utilizing a set pulse SET for controlling the timing of the rise of the output OUT and a reset pulse RESET for controlling the timing of the fall of the output OUT and by propagating the control pulses SET and RESET respectively via the inverters in multi-stage structures. As shown in FIG. 3, the NOR gate 10 at the last stage consists of transistors P17, P18, N19 and N20.
The inverters in each inverter array consist of alternately combined imbalance-sized transistors and, in the figure, the large-sized transistors are depicted large and the small-sized transistors are depicted small. The leading edge of the set pulse SET is propagated through nodes n11, n12 and n13 in an inverter array INV10-12 and drives a transistor P17 of the NOR gate at the last stage to activate the output OUT. On the other hand, the leading edge of the reset pulse RESET being delayed by the amount of the output pulse width from the set pulse SET is also propagated through nodes n14, n15 and n16 in an inverter array INV15-17 and drives a transistor N20 of the NOR gate at the last stage to deactivate the output OUT.
By providing the reset pulse RESET and the inverter array INV15-17 for propagating it and driving the gate 10 at the last stage, the fall of the output pulse OUT can be controlled and the delay of the fall of the output pulse can be minimized through using not the trailing edge of the set pulse SET but the leading edge of the reset pulse RESET.
By replacing the NOR gate 10 at the last stage of this pulse generation circuit with a NAND gate and an inverter, a similar pulse generation circuit can also be constituted. In such case, the phase of the control pulse is inverted.
FIG. 5 illustrates yet another conventional pulse generation circuit. The operational waveform of the pulse generation circuit shown in FIG. 5 is illustrated in FIG. 4. The pulse generation circuit shown in FIG. 5 has an output stage gate circuit 12 consisting of a p-channel transistor P30 and an N-channel transistor N31 instead of the NOR gate 10 at the last stage in the pulse generation circuit shown in FIG. 3.
In this pulse generation circuit, the output pulse OUT is raised to an activation level (H level) by propagating the leading edge of the set pulse SET to drive the transistor P30 at the last stage. The output pulse OUT is fallen to a deactivation level (L level) by propagating the leading edge of the reset pulse RESET to drive the transistor N31 at the last stage. Therefore, this pulse generation circuit can also prevent the fall of the output pulse of the pulse generation circuit from being delayed by the process variations as shown in FIG. 1.
The pulse generation circuit shown in FIG. 3 has a last stage that is a NOR gate or a NAND gate. When it is a NOR gate, as shown in FIG. 3, the circuit for raising the output pulse consists of the transistors P17 and P18 connected in series and the output pulse is raised when these transistors become conductive. Therefore, this pulse generation circuit has a problem that the drive capability can not be enhanced so much, even though enlarging the size of the transistors P17 and P18, due to the influence of the series resistance of these transistors when driving the output terminal OUT. Furthermore, it is necessary for the size of the four transistors in the NOR gate to be made large and there is another problem that the area of the circuit becomes large comparing to an inverter.
Similarly, even when the last stage consists of a combination of a NAND gate and an inverter, the circuit for decreasing the output of the NAND gate is a circuit consisting of two n-channel transistors connected in series and the drive capability of the circuit for decreasing the outout of the NAND gate is lowered due to the series resistance of the circuit as is the NOR gate. Furthermore, a problem that the area of the circuit becomes large arises when the size of all the output stage transistors whose number is increased is madelarge.
On the other hand, since the pulse generation circuit shown in FIG. 5 has an output stage gate structured as an inverter consisting of two transistors, there is no problem of the increase of the area of the circuit or the lowering of the drive capability, as with the pulse generation circuit shown in FIG. 3. However, as shown in FIG. 4, the trailing edge of the set pulse SET is delayed while propagating through the nodes n11, n12 and n13 because of being influenced by the process variation due to the imbalance sizes of the transistors of the inverters INV10-12. As a result, the L level at the node n13 and the H level at the node n16 overlap each other at a time dt2, both of the transistors P30 and N31 at the output stage gate 12 become conductive and a penetrating current flows. Since the size of the transistors at the output stage gate 12 is large, this penetrating current is not preferable because it results in an increase of power consumption.
Therefore, it is necessary to delay the timing of the leading edge of the reset pulse to prevent this penetrating current and, as a result, the pulse width of the output pulse can not be narrowed and the cycle of the output pulse can not be shortened. The pulse width of the output pulse can not be made narrower than the pulse width of the set pulse. Furthermore, because the trailing edge of the set pulse is delayed by the process variations, the pulse width of the output pulse can not be narrowed due to the delay.
The object of the invention is to provide a pulse generation circuit that can shorten the cycle of the output pulse generated in response to a control pulse and that can generate the output pulse without delay to the control pulse.
In order to achieve the above object, according to an aspect of the present invention, there is provided a pulse generation circuit for generating an output pulse that is set to its activated level in response to a leading edge of a set pulse, the pulse generation circuit comprising an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, including a plurality of inverters connected in series, for propagating the set pulse and driving the first output transistor; a second inverter array, including a plurality of inverters connected in series, for propagating a reset pulse controlling the deactivation of the output pulse and for driving the second output transistor. To prevent the pulse edge corresponding to the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, for driving the pulse edge at the inverter output corresponding to the trailing edge of the set pulse, in response to the reset pulse propagating through the second inverter array.
According to the aspect of the invention, since a reset transistor drives the trailing edge of the propagating set pulse in response to the reset pulse, the trailing edge of the propagating set pulse is prevented from being delayed due to the inverters of the first inverter array. Therefore, the reset pulse can be generated from the leading edge of the set pulse at an earlier timing and the pulse width of the output pulse can be narrowed so as to shorten the cycle of the output pulse.
In a preferred embodiment of the invention, each of inverters in the first inverter array has a first inverter transistor for driving the pulse edge corresponding to the leading edge of the set pulse and a second inverter transistor smaller in size than the first inverter transistor, for driving the pulse edge corresponding to the trailing edge of the set pulse, and the reset transistor is provided in parallel to the second inverter transistor.
In this embodiment, transistors in each inverter in a first inverter array are in imbalance structures and the propagation velocity of the leading edge of the set pulse can be increased. However, the delay of the trailing edge of the set pulse can be prevented by reset transistors.
In another preferred embodiment of the invention, each of inverters in the first inverter array has a first inverter transistor for driving a pulse edge corresponding to the leading edge of the set pulse, and the reset transistor is provided at the power supply side opposite to the first inverter transistor. Being different from the above embodiment, this embodiment does not have the second inverter transistor for driving the pulse edge corresponding to the trailing edge of the set pulse.
In this embodiment, the propagation velocity of the leading edge of the set pulse can be increased and the second inverter transistor can be omitted. Therefore, the scale of the circuit can be made small.